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m12l16161a elite semiconductor memory technology inc. p. 1 publication date : jan. 2000 revision : 1.3u 512k x 16bit x 2banks synchronous dram features z jedec standard 3.3v power supply z lvttl compatible with multiplexed address z dual banks operation z mrs cycle with address key programs - cas latency (2 & 3 ) - burst length (1, 2, 4, 8 & full page) - burst type (sequential & interleave) z all inputs are sampled at the positive going edg e of the system clock z burst read single-bit write operation z dqm for masking z auto & self refresh z 32ms refresh period (2k cycle) general description the m12l16161a is 16,777,216 bits synchro- nous high data rate dynamic ram organized as 2 x 524,288 words by 16 bits, fabricated with high performance cmos technology. synchro- nous design allows precise cycle control with the use of system clock i/o transactions are possible on every clock cycle. range of operating fre- quencies, programmable burst length and pro- grammable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ordering information part no. max freq. interface package m12l16161a-4.3t 233mhz m12l16161a-5t 200mhz m12l16161a-5.5t 183mhz M12L16161A-6T 166mhz m12l16161a-7t 143mhz m12l16161a-8t 125mhz lv tt l 50 tsop(ii) pin configuration (top view) v dd dq0 dq1 v ssq dq2 dq3 v ddq dq4 dq5 v ssq dq6 dq7 v ddq ldqm we cas ras cs ba a10/ap a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v ss dq15 dq14 v ssq dq13 dq12 v ddq dq11 dq10 v ssq dq9 dq8 v ddq n.c/rfu udqm clk cke n.c a9 a8 a7 a6 a5 a4 v ss 50pin tsop(ii) (400mil x 825mil) (0.8 mm pin pitch)
m12l16161a elite semiconductor memory technology inc. p. 2 publication date : jan. 2000 revision : 1.3u functional block diagram pin function description pin name input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and l(u)dqm. cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. a0 ~ a10/ap address row / column addresses are multiplexed on the same pins. row address : ra0 ~ ra10, column address : ca0 ~ ca7 ba bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. latches data in starting from cas , we active. l(u)dqm data input / output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when l(u)dqm active. dq 0 ~ 15 data input / output data inputs/outputs are multiplexed on the same pins. v dd /v ss power supply/ground power and ground for the input buffers and the core logic. bank select data input register column decoder latency & burst length programming register 512k x 16 512k x 16 timing register sense amp clk cke cs ras cas we l(u)dqm ldqm lwcbr dqi ldqm lwe col. buffer lras lcbr lras lcbr lwe lcas clk add lcke output buffer address register row buffer refresh counter row decoder i/o control
m12l16161a elite semiconductor memory technology inc. p. 3 publication date : jan. 2000 revision : 1.3u v ddq /v ssq data output power/ground isolated power supply and ground for the output buffers to provide improved noise immunity. n.c/rfu no connection/ reserved for future use this pin is recommended to be left no connection on the device. absolute maximum ratings parameter symbol va l ue unit voltage on any pin relative to v ss v in, v out -1.0 ~ 4.6 v voltage on v dd supply relative to v ss v dd ,v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ + 150 c power dissipation p d 1w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. dc operating conditions recommended operating conditions (voltage referenced to vss = 0v, ta=0 to 70 c ) parameter symbol min typ max unit note supply voltage v dd ,v ddq 3.0 3.3 3.6 v input logic high voltage v ih 2.0 3.0 v dd +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh =-2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i il -5 - 5 ua 3 output leakage current i ol -5 - 5 ua 4 note : 1.v ih (max) = 4.6v ac for pulse width 10ns acceptable. 2.v il (min) = -1.5v ac for pulse width 10ns acceptable. 3.any input 0v v in v dd + 0.3v, all other pins are not under test = 0v. 4.dout is disabled, 0v v out v dd . capacitance (v dd = 3.3v, t a = 25 c , f = 1mhz) pin symbol min max unit clock c clk 2.5 4.0 pf ras , cas , we , cs , cke, ldqm, udqm c in 2.5 5.0 pf address c add 2.5 5.0 pf dq0 ~dq15 c out 4.0 6.5 pf
m12l16161a elite semiconductor memory technology inc. p. 4 publication date : jan. 2000 revision : 1.3u dc characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70 c v ih (min)/v il (max)=2.0v/0.8v) version parameter symbol test condition cas latency -4.3 -5 -5.5 -6 -7 -8 unit note operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min), t cc 3 t cc (min), i ol = 0ma 250 230 210 190 160 140 ma 1 i cc2 p cke v il (max), t cc =15ns 2 ma precharge standby current in power-down mode i cc2 ps cke v il (max), clk v il (max), t cc = 2 i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc =15ns input signals are changed one time during 30ns 30 ma precharge standby current in non power- down mode i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 2ma i cc3 p cke v il (max), t cc =15ns 10 active standby current in power-down mode i cc3 ps cke v il (max), clk v il (max), t cc = 10 ma i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc =15ns input signals are changed one time during 30ns 40 ma active standby current in non power-down mode (one bank active) i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 10 ma 3 270 250 230 210 180 160 ma 1 operating current (burst mode) i cc 4 i ol = 0ma, page burst all band activated, t ccd = t ccd (min) 2 270 250 230 210 180 160 refresh current i cc 5 t rc 3 t rc (min) 270 250 230 210 180 160 ma 2 self refresh current i cc 6cke 0.2v 1 ma note: 1.measured with outputs open. addresses are changed only one time during t cc (min). 2.refresh period is 32ms. addresses are changed only one time during t cc (min).
m12l16161a elite semiconductor memory technology inc. p. 5 publication date : jan. 2000 revision : 1.3u ac operating test conditions (v dd =3.3v 0.3v,t a = 0 to 70 c ) parameter va l ue unit input levels (vih/vil) 2.4 / 0.4 v input timing measurement reference level 1.4 v input rise and fall time tr / tf = 1 / 1 ns output timing measurement reference level 1.4 v output load condition see fig.2 operating ac parameter (ac operating conditions unless otherwise noted) version parameter symbol -4.3 -5 -5.5 -6 -7 -8 unit note row active to row active delay t rrd (min) 8.61011121416 ns 1 ras to cas delay t rcd (min) 12.91516161620 ns 1 row precharge time t rp (min) 12.91516182020 ns 1 t ras (min) 34.44040424248 ns 1 row active time t ras (max) 100 us row cycle time t rc (min) 47.35560606368 ns 1 last data in to new col. address delay t cdl (min) 1clk2 last data in to row precharge t rdl (min) 1clk2 last data in to burst stop t bdl (min) 1clk2 col. address to col. address delay t ccd (min) 1clk3 cas latency=3 1 number of valid output data cas latency=2 1 ea 4 note: 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 4. minimum delay is required to complete write. 4. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. the earliest a precharge command can be issued after a read command without the loss of data is cl+bl-2 clocks. 3 . 3 v o u t p u t ( f i g . 2 ) a c o u t p u t l o a d c i r c u i t 3 0 p f v t t = 1 . 4 v v o h ( d c ) = 2 . 4 v , i o h = - 2 m a v o l ( d c ) = 0 . 4 v , i o l = 2 m a 3 0 p f o u t p u t ( f i g . 1 ) d c o u t p u t l o a d c i r c u i t z 0 = 5 0 8 7 0 1 2 0 0 5 0
m12l16161a elite semiconductor memory technology inc. p. 6 publication date : jan. 2000 revision : 1.3u ac characteristics (ac operating conditions unless otherwise noted) -4.3 -5 -5.5 -6 -7 -8 parameter symbol min max min max min max min max min max min max unit note cas latency =3 4.3 5 5.5 6 7 8 clk cycle time cas latency =2 t cc 6 1000 7 1000 7.5 1000 8 1000 8.6 1000 10 1000 ns 1 cas latency =3 - 4 - 4.5 - 5 - 5.5 - 6 - 6 clk to valid output delay cas latency =2 t sac - 5 - 5 - 6 - 6 - 6 - 7 ns 1 output data hold time t oh 2 2 2.5 2.5 2.5 2.5 ns 2 clk high pulse width t ch 1.7 2 2 2 2.5 3 ns 3 clk low pulse width t cl 1.7 2 2 2 2.5 3 ns 3 input setup time t ss 1.7 2 2 2 2 2.5 ns 3 input hold time t sh 1 1 1 1 1 1 ns 3 clk to output in low-z t slz 1 1 1 1 1 1 ns 2 cas latency =3 - 4 -4.5 - 5 - 5.5 - 6 - 6 clk to output in hi-z cas latency =2 t shz - 5 - 5 - 6 - 6 - 6 - 7 ns *all ac parameters are measured from half to half. note: 1.parameters depend on programmed cas latency. 2.if clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3.assumed input rise and fall time (tr & tf)=1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter.
m12l16161a elite semiconductor memory technology inc. p. 7 publication date : jan. 2000 revision : 1.3u frequency vs. ac paramenter relationahip table m12l16161a-4.3t (unit: number of clock) trc tras trp trrd trcd tccd tcdl trdl frequency cas latency 47.3ns 34.3ns 12.9ns 8.6ns 12.9ns 4.3ns 4.3ns 4.3ns 233mhz(4.3ns) 3 11 8323111 200mhz(5.0ns) 3 10 7323111 183mhz(5.5ns) 3 10 7323111 166mhz(6.0ns) 3 96323111 143mhz(7.0ns) 2 75222111 m12l16161a-5t (unit: number of clock) trc tras trp trrd trcd tccd tcdl trdl frequency cas latency 55ns 40ns 15ns 10ns 15ns 5ns 5ns 5ns 200mhz(5.0ns) 3 11 8323111 183mhz(5.5ns) 3 10 8323111 166mhz(6.0ns) 3 10 7323111 143mhz(7.0ns) 2 96323111 125mhz(8.0ns) 2 75222111 111mhz(9.0ns) 2 75222111 m12l16161a-5.5t (unit: number of clock) trc tras trp trrd trcd tccd tcdl trdl frequency cas latency 60ns 40ns 16ns 11ns 16ns 5.5ns 5.5ns 5.5ns 183mhz(5.5ns) 3 11 8323111 166mhz(6.0ns) 3 10 7323111 143mhz(7.0ns) 2 96323111 125mhz(8.0ns) 2 85222111 111mhz(9.0ns) 2 75222111 M12L16161A-6T (unit: number of clock) trc tras trp trrd trcd tccd tcdl trdl frequency cas latency 60ns 42ns 18ns 12ns 16ns 6ns 6ns 6ns 166mhz(6.0ns) 3 10 7323111 143mhz(7.0ns) 3 96323111 125mhz(8.0ns) 2 96322111 111mhz(9.0ns) 2 75222111 100mhz(10.0ns) 2 75222111 m12l16161a-7t (unit: number of clock) trc tras trp trrd trcd tccd tcdl trdl frequency cas latency 62ns 42ns 20ns 14ns 16ns 7ns 7ns 7ns 143mhz(7.0ns) 3 96323111 125mhz(8.0ns) 3 96322111 111mhz(9.0ns) 2 85322111 100mhz(10.0ns) 2 75222111 83mhz(12.0ns) 2 64222111 m12l16161a-8t (unit: number of clock) trc tras trp trrd trcd tccd tcdl trdl frequency cas latency 68ns 48ns 20ns 16ns 20ns 8ns 8ns 8ns 125mhz(8.0ns) 3 96323111 111mhz(9.0ns) 3 96323111 100mhz(10.0ns) 2 75222111 83mhz(12.0ns) 2 64222111 75mhz(13.0ns) 2 64222111
m12l16161a elite semiconductor memory technology inc. p. 8 publication date : jan. 2000 revision : 1.3u mode register 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 jedec standard test set (refresh counter test) 11 10 9 8 7 6 5 4 3 2 1 0 x x 1 0 0 ltmode wt bl burst read and single write (for write through cache) 11 10 9 8 7 6 5 4 3 2 1 0 1 0 use in future 11 10 9 8 7 6 5 4 3 2 1 0 x x x 1 1 v v v v v v v vender specific 11 10 9 8 7 6 5 4 3 2 1 0 v =valid 0 0 0 0 0 ltmode wt bl mode register set x =dont care bit2-0 wt=0 wt=1 000 1 1 001 2 2 010 4 4 011 8 8 100 r r 101 r r 110 r r burst length 111 full page r 0 sequential wrap type 1 interleave bits6-4 cas latency 000 r 001 r 010 2 011 3 100 r 101 r 110 r latency mode 111 r mode register write timing remark r : reserved m o d e r e g i s t e r w r i t e c l o c k c k e c s r a s w e a 0 - a 1 1 c a s
m12l16161a elite semiconductor memory technology inc. p. 9 publication date : jan. 2000 revision : 1.3u burst length and sequence (burst of two) starting address (column address a0 binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00,10,1 11,01,0 (burst of four) starting address (column address a1-a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00 0,1,2,3 0,1,2,3 01 1,2,3,0 1,0,3,2 10 2,3,0,1 2,3,0,1 11 3,0,1,2 3,2,1,0 (burst of eight) starting address (column address a2-a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6 010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2 110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1 111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0 full page burst is an extension of the above tables of sequential addressing, with the length being 256 for 1mx16 divice. power up sequence 1.apply power and start clock, attempt to maintain cke= h, l(u)dqm = h and the other pin are nop condition at the inputs. 2.maintain stable power, stable clock and nop input condition for a minimum of 200us. 3.issue precharge commands for all banks of the devices. 4.issue 2 or more auto-refresh commands. 5.issue mode register set command to initialize the mode register. cf.)sequence of 4 & 5 is regardless of the order.
m12l16161a elite semiconductor memory technology inc. p. 10 publication date : jan. 2000 revision : 1.3u simplified truth table command cken-1 cken cs ras cas we dqm ba a10/ap a9~a0 note register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l ll l h x x 3 lhhh 3 refresh self refresh exit l h hxxx xx 3 bank active & row addr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge enable hxlhlhxv h column address (a0~a7) 4,5 auto precharge disable l4 write & column address auto precharge enable hxlhllxv h column address (a0~a7) 4,5 burst stop h x l h h l x x 6 bank selection v l 4 precharge both banks hxllhlx xh x 4 hxxx entry h l lvvv x clock suspend or active power down exit l hxxxxx x hxxx entry h l lhhh x hxxx precharge power down mode exit l h lvvv x x dqm h x v x 7 h hxxx no operation command h x lhhh xx (v= valid, x= dont care, h= logic high , l = logic low) note:1 op code: operation code a0~ a10/ap, ba: program keys.(@mrs) 2. mrs can be issued only at both banks precharge state. a new command can be issued after 2 clock cycle of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by auto. auto / self refresh can be issued only at both banks precharge state. 4. ba: bank select address. if low: at read, write, row active and precharge, bank a is selected. if high: at read, write, row active and precharge, bank b is selected. if a10/ap is high at row precharge, ba ignored and both banks are selected. 5.during burst read or write with auto precharge, new read/write command can not be issued. another bank read /write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6.burst stop command is valid at every burst length. 7.dqm sampled at pos itive going edge of a clk masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2)
m12l16161a elite semiconductor memory technology inc. p. 11 publication date : jan. 2000 revision : 1.3u single bit read-write-read cycle (same page) @cas latency=3, burst length=1 : d o n ' t c a r e 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 c l o c k c k e c s r a s c a s a d d r w e d q d q m a 1 0 / a p t c h t c l t c c r o w a c t i v e b a * n o t e 1 h i g h t r c d t s s t s s t s h t s h t s s t s h t s s t s s t s h t s s t s s t s h r a c a c b c c r b b s b s b s b s b s b s r a q a d b q c r b r e a d w r i t e r e a d p r e c h a r g e r o w a c t i v e t r c t r a s t r p t c c d t r a c * n o t e 2 * n o t e 2 , 3 * n o t e 4 * n o t e 2 * n o t e 2 , 3 * n o t e 3 * n o t e 3 * n o t e 2 , 3 t s h t s l z t s a c t o h t s h t s h t s s * n o t e 4 * n o t e 3
m12l16161a elite semiconductor memory technology inc. p. 12 publication date : jan. 2000 revision : 1.3u *note: 1. all inputs expect cke & dqm can be dont care when cs is high at the clk high going edge. 2. bank active & read/write are controlled by ba. ba active & read/write 0bank a 1bank b 3.enable and disable auto precharge function are controlled by a10/ap in read/write command. a10/ap ba operation 0 disable auto precharge, leave bank a active at end of burst. 0 1 disable auto precharge, leave bank b active at end of burst. 0 enable auto precharge, precharge bank a at end of burst. 1 1 enable auto precharge, precharge bank b at end of burst. 4.a10/ap and ba control bank precharge when precharge command is asserted. a10/ap ba precharge 00 bank a 01 bank b 1 x both banks
m12l16161a elite semiconductor memory technology inc. p. 13 publication date : jan. 2000 revision : 1.3u power up sequence 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 c l o c k c k e a d d r d q d q m a 1 0 / a p t r p k e y r a a r a a p r e c h a r g e a l l b a n k s a u t o r e f r e s h a u t o r e f r e s h m o d e r e g i s t e r s e t ( a - b a n k ) r o w a c t i v e : d o n ' t c a r e t r c t r c h i g h l e v e l i s n e c e s s a r y h i g h l e v e l i s n e c e s s a r y b a h i g h - z c s r a s c a s w e k e y k e y
m12l16161a elite semiconductor memory technology inc. p. 14 publication date : jan. 2000 revision : 1.3u read & write cycle at same bank @burst length = 4 *note: 1.minimum row cycle times is required to complete internal dram operation. 2.row precharge can interrupt burst on any cycle. [cas latency-1] number of valid output data is available after row precharge. last valid output will be hi-z( t shz ) after the clock. 3.access time from row active command. tcc* (t rcd +cas latency-1)+ t sac 4.ouput will be hi-z after the end of burst.(1,2,4,8 bit burst) burst cant end in full page mode. t r c d t r c 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 c l o c k c k e c s r a s c a s a d d r d q m b a c l = 2 c l = 3 r a r b c b 0 t o h t s a c t s h z t s h z t r d l r e a d r o w a c t i v e p r e c h a r g e ( a - b a n k ) ( a - b a n k ) ( a - b a n k ) p r e c h a r g e ( a - b a n k ) w r i t e ( a - b a n k ) r o w a c t i v e ( a - b a n k ) * n o t e 3 * n o t e 3 * n o t e 4 * n o t e 4 : d o n ' t c a r e * n o t e 1 q a 0 q a 1 q a 2 q a 3 d b 0 d b 3 d b 1 d b 2 q a 0 q a 1 q a 2 q a 3 d b 0 d b 3 d b 1 d b 2 t r a c t r a c t r d l c a 0 a 1 0 / a p r a r b h i g h * n o t e 2 w e t o h t s a c q c
m12l16161a elite semiconductor memory technology inc. p. 15 publication date : jan. 2000 revision : 1.3u page read & write cycle at same bank @ burst length=4 *note : 1.to write data before burst read ends, dqm should be asserted three cycle prior to write command to avoid bus contention. 2.row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3.dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 c l o c k c k e c s r a s c a s b a a d d r a 1 0 / a p c l = 2 c l = 3 w e d q m h i g h t r c d * n o t e 2 r a c a 0 c b 0 c c 0 c d 0 r a q a 0 q a 1 q b 0 q b 1 q b 2 d c 0 d c 1 d d 0 d d 1 q a 0 q a 1 q b 1 q b 2 d c 0 d c 1 d d 0 d d 2 t c d l * n o t e 1 r o w a c t i v e ( a - b a n k ) r e a d ( a - b a n k ) r e a d ( a - b a n k ) w r i t e ( a - b a n k ) w r i t e ( a - b a n k ) p r e c h a r g e ( a - b a n k ) : d o n ' t c a r e d q 01 2 t r d l * n o t e 3
m12l16161a elite semiconductor memory technology inc. p. 16 publication date : jan. 2000 revision : 1.3u page read cycle at different bank @ burst length=4 *note: 1. cs can be dont cared when ras , cas and we are high at the clock high going dege. 2.to interrupt a burst read by row precharge, both the read and the precharge banks must be the same. 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 clock cke cs ras cas ba addr a10/ap cl=2 cl=3 we dqm h i g h * n o t e 2 r a a c a a r b b r a a r e a d ( a - b a n k ) r o w a c t i v e r o w a c t i v e ( b - b a n k ) ( a - b a n k ) r e a d ( a - b a n k ) r e a d ( b - b a n k ) r e a d ( a - b a n k ) r e a d ( b - b a n k ) p r e c h a r g e ( a - b a n k ) : d o n ' t c a r e dq 01 2 c b b c a c c b d c a e q a a 0 q a a 1 q a a 2 q a a 3 q b b 0 q b b 1 q b b 2 q b b 3 q a c 0 q a c 1 q b d 0 q b d 1 q a e 0 q a e 1 q a a 0 q a a 1 q a a 2 q a a 3 q b b 0 q b b 1 q b b 2 q b b 3 q a c 0 q a c 1 q b d 0 q b d 1 q a e 0 q a e 1 * n o t e 1 r b b
m12l16161a elite semiconductor memory technology inc. p. 17 publication date : jan. 2000 revision : 1.3u page write cycle at different bank @burst length = 4 *note: 1.to interrupt burst write by row precharge, dqm should be asserted to mask invalid input data. 2.to interrupt burst write by row precharge, both the write and the precharge banks must be the same. 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 c l o c k c k e c s r a s c a s b a a d d r a 1 0 / a p w e d q m h i g h r o w a c t i v e ( a - b a n k ) r o w a c t i v e ( b - b a n k ) w r i t e ( a - b a n k ) p r e c h a r g e ( b o t h b a n k s ) : d o n ' t c a r e d q w r i t e ( a - b a n k ) w r i t e ( b - b a n k ) w r i t e ( b - b a n k ) d a a 0 d a a 1 d a a 2 d a a 3 d b b 0 d b b 1 d b b 2 d b b 3 d a c 0 d a c 1 d b d 0 d b d 1 r a a r b b r a a c a a r b b c b b c a c c b d * n o t e 2 t c d l t r d l * n o t e 1
m12l16161a elite semiconductor memory technology inc. p. 18 publication date : jan. 2000 revision : 1.3u read & write cycle at different bank @ burst length = 4 *note: 1. t cdl should be met to complete write. clock cke cs ras cas addr we dqm a10/ap cl=2 cl=3 row active (a-bank) read (a-bank) : d o n ' t c a r e qaa1 qaa2 qaa3 dbb1 dbb2 dbb3 dbb0 qaa0 raa cac raa caa qaa1 qaa2 qaa3 dbb1 dbb2 dbb3 dbb0 qaa0 write (b-bank) high rbb cbb rac rbb rac qac0 qac1 qac2 qac0 qac1 read (a-bank) row active (b-bank) precharge (a-bank) row active (a-bank) t cdl *note1 1 9 2 10 3 4 5 6 7 8 11 12 13 14 17 15 18 16 19 0 ba dq rbb
m12l16161a elite semiconductor memory technology inc. p. 19 publication date : jan. 2000 revision : 1.3u read & write cycle with auto precharge @ burst length =4 *note: 1. t cdl should be controlled to meet minimum t ras before internal precharge start (in the case of burst length=1 & 2 and brsw mode) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 c l o c k c k e c a s a d d r w e d q d q m a 1 0 / a p b a c l = 2 c l = 3 r o w a c t i v e ( a - b a n k ) r o w a c t i v e ( b - b a n k ) r e a d w i t h a u t o p r e c h a r g e ( a - b a n k ) a u t o p r e c h a r g e s t a r t p o i n t ( b - b a n k ) : d o n ' t c a r e q a 1 q a 2 q a 3 d b 1 d b 2 d b 3 d b 0 q a 0 r a c b r a c a r b r b q a 1 q a 2 q a 3 d b 1 d b 2 d b 3 d b 0 q a 0 w r i t e w i t h a u t o p r e c h a r g e ( b - b a n k ) h i g h a u t o p r e c h a r g e s t a r t p o i n t ( a - b a n k ) c s r a s c l = 2 a u t o p r e c h a r g e s t a r t p o i n t ( a - b a n k ) c l = 3
m12l16161a elite semiconductor memory technology inc. p. 20 publication date : jan. 2000 revision : 1.3u clock suspension & dqm operation cycle @cas latency=2, burst length=4 *note:1.dqm is needed to prevent bus contention. c l o c k c k e a d d r d q d q m a 1 0 / a p r a c a c b c c r a q a 0 q a 1 q a 2 q a 3 t s h z q b 1 q b 0 t s h z d c 0 d c 2 * n o t e 1 r o w a c t i v e r e a d c l o c k s u s p e n s i o n r e a d r e a d d q m w r i t e w r i t e d q m c l o c k s u s p e n s i o n w r i t e d q m : d o n ' t c a r e 1 9 2 1 0 3 4 5 6 7 8 1 1 1 2 1 3 1 4 1 7 1 5 1 8 1 6 1 9 0 b a c s r a s c a s w e
m12l16161a elite semiconductor memory technology inc. p. 21 publication date : jan. 2000 revision : 1.3u read interrupted by precharge command & read burst stop cycle @burst length =full page *note: 1.burst cant end in full page mode, so auto precharge cant issue. 2.about the valid dqs after burst stop, it is same as the case of ras interrupt. both cases are illustrated above timing diagram. see the label 1,2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of full page write burst stop cycle. 3.burst stop is valid at every burst length. 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 clock cke addr dq dqm a10/ap ba raa caa cab raa q a a 0 q a a 1 q a b 1 q a b 0 q a b 2 *note1 row active (a-bank) read (a-bank) burst stop read (a-bank) :don't care high cl=2 cl=3 q a a 2 q a a 3 q a a 4 q a b 3 q a b 4 q a b 5 q a a 0 q a a 1 q a b 1 q a b 0 q a b 2 q a a 2 q a a 3 q a a 4 q a b 3 q a b 4 q a b 5 1 1 2 2 precharge (a-bank) cs ras cas we * n o t e 2
m12l16161a elite semiconductor memory technology inc. p. 22 publication date : jan. 2000 revision : 1.3u write interrupted by precharge command & write burst stop cycle @ burst length =full page *note: 1. burst cant end in full page mode, so auto precharge cant issue. 2.data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. it is defined by ac parameter of t rdl . dqm at write interrupted by precharge command is needed to prevent inv alid write. input data after row precharge cycle will be masked internally. 3.burst stop is valid at every burst length. clock cke addr dq dqm a10/ap raa caa cab raa daa0 daa1 dab1 dab0 dab2 row active (a-bank) w rite (a-bank) burst stop write (a-bank) :don't care high daa2 daa3 daa4 dab3 dab4 dab5 precharge (a-bank) t bdl t rdl *note2 1 9 210 3 4 5 6 78 11 12 13 14 17 15 18 16 19 0 cs ras cas we ba
m12l16161a elite semiconductor memory technology inc. p. 23 publication date : jan. 2000 revision : 1.3u burst read single bit write cycle @burst length=2 *note:1.brsw modes is enabled by setting a9 high at mrs(mode register set). at the brsw mode, the burst length at write is fixed to 1 regardless of programmed burst length. 2.when brsw write command with auto precharge is executed, keep it in mind that t ras should not be violated. auto precharge is executed at the next cycle of burst-end, so in the case of brsw write command, the precharge command will be issued after two clock cycles. c l o c k c k e a d d r c l = 2 d q m a 1 0 / a p b a r a a r a c r a a q a b 0 r o w a c t i v e ( a - b a n k ) w r i t e ( a - b a n k ) : d o n ' t c a r e h i g h q a b 1 p r e c h a r g e ( a - b a n k ) c a a r b b c a b c b c c a d r a c d b c 0 d q d a a 0 q a b 0 d b c 0 q a b 1 c l = 3 r o w a c t i v e ( b - b a n k ) r o w a c t i v e ( a - b a n k ) w r i t e w i t h a u t o p r e c h a r g e ( b - b a n k ) r e a d ( a - b a n k ) 1 9 2 1 0 3 4 5 6 7 8 1 1 1 2 1 3 1 4 1 7 1 5 1 8 1 6 1 9 0 d a a 0 q a d 0 q a d 1 q a d 0 q a d 1 * n o t e 1 c s r a s c a s w e r b b * n o t e 2 r e a d w i t h a u t o p r e c h a r g e ( a - b a n k )
m12l16161a elite semiconductor memory technology inc. p. 24 publication date : jan. 2000 revision : 1.3u active/precharge power down mode @cas latency=2, burst length=4 *note : 1.both banks should be in idle state prior to entering precharge power down mode. 2.cke should be set high at least 1clk+tss prior to row active command. 3.can not violate minimum refresh specification. (32ms) c l o c k c k e a d d r d q d q m a 1 0 / a p a c t i v e p o w e r - d o w n e x i t p r e c h a r g e : d o n ' t c a r e * n o t e 3 * n o t e 2 * n o t e 1 t s s r a r a q a 0 q a 1 q a 2 t s h z p r e c h a r g e p o w e r - d o w n e n t r y p r e c h a r g e p o w e r - d o w n e x i t r o w a c t i v e a c t i v e p o w e r - d o w n e n t r y r e a d c a b a r a s c a s c s w e t s s 1 9 2 1 0 3 4 5 6 7 8 1 1 1 2 1 3 1 4 1 7 1 5 1 8 1 6 1 9 0 t s s
m12l16161a elite semiconductor memory technology inc. p. 25 publication date : jan. 2000 revision : 1.3u self refresh entry & exit cycle *note: to enter self refresh mode 1. cs , ras & cas with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock can be dont care except for cke. 3. the device remains in self refresh mode as long as cke stays low. cf.) once the device enters self refresh mode, minimum t ras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. cs starts from high. 6. minimum t rc is required after cke going high to complete self refresh exit. 7.2k cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. c l o c k c k e a d d r d q d q m a 1 0 / a p s e l f r e f r e s h e n t r y a u t o r e f r e s h : d o n ' t c a r e s e l f r e f r e s h e x i t h i - z h i - z w e b a c a s r a s c s * n o t e 2 * n o t e 1 * n o t e 4 t r c m i n * n o t e 6 * n o t e 5 * n o t e 7 0 1 2 3 4 5 6 8 7 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 t s s * n o t e 3
m12l16161a elite semiconductor memory technology inc. p. 26 publication date : jan. 2000 revision : 1.3u mode register set cycle auto refresh cycle *both banks precharge should be completed before mode register set cycle and auto refresh cycle. mode register set cycle *note: 1. cs , ras , cas & we activation at the same clock cycle with address key will set internal mode register. 2.minimum 2 clock cycles should be met before new ras activation. 3.please refer to mode register set table. c l o c k c k e a d d r k e y : d o n ' t c a r e h i g h c s r a s c a s h i g h * n o t e 3 r a * n o t e 1 d q h i - z d q m 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 1 0 h i - z * n o t e 2 t r f c m r s n e w c o m m a n d a u t o r e f r e s h n e w c o m m a n d w e 0
m12l16161a elite semiconductor memory technology inc. p. 27 publication date : jan. 2000 revision : 1.3u package dimensions 50-lead tsop(ii) sdram(400mil) dimension in mm dimension in inch symbol min nom max min nom max a - - 1.20 - - 0.047 a1 0.05 0.10 0.15 0.002 0.004 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.30 - 0.45 0.012 - 0.018 b1 0.30 0.35 0.40 0.012 0.014 0.016 c 0.12 - 0.21 0.005 - 0.008 c1 0.10 0.127 0.16 0.004 0.005 0.006 d 20.82 20.95 21.08 0.820 0.825 0.830 zd 0.875 ref 0.034 ref e 11.56 11.76 11.96 0.455 0.463 0.471 e1 10.03 10.16 10.29 0.394 0.400 0.405 l 0.40 0.50 0.60 0.016 0.020 0.024 l1 0.80 ref 0.031 ref 0.80 bsc 0.031 bsc r1 0.12 - - 0.005 - r2 0.12 - 0.25 0.005 - 0.010 e 0-80-8 e 2 0--0-- e 3 10 15 20 10 15 20 e 10 15 20 10 15 20 ee 1 1 25 50 26 8.78 2.91 d o1.5 (zd) e -c- seating plane b 0.10 c -c- a 2 a -h- detail a -c- a 1 o 2 (4x) o (4x) 3 r 1 b b r 2 o plane gage 1 o l detail a l 1 b 1 b c 1 c section b-b with plating base metal 0.665 ref 0.21 ref .25

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